1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to an semiconductor integrated circuit device that allows power consumption to be reduced in a standby state.
2. Description of the Background Art
FIG. 17 is a circuit diagram showing main components of a logic gate circuit in a conventional semiconductor integrated circuit device 1000.
It is assumed that the semiconductor integrated circuit device of FIG. 17 attains a standby state.
FIG. 17 exemplifies a logic gate in which a plurality of stages of inversion circuits are connected in series.
More specifically, inverters 1010-1040 are connected in series with each other. Each inverter circuit is supplied with a voltage from a power supply potential Vcc and connected to a ground potential (GND).
It is assumed that the input to inverter circuit 1010 attains an L level (logical low) in a standby state. Therefore, the input to inverter 1020 attains an H level (logical high), the input to inverter 1030 attains an L level, and the input to inverter 1040 attains an H level in a standby state. Also, a signal of an L level is provided from inverter 1040.
Inverter 1010 includes a P channel MOS transistor 1012 and an n channel MOS transistor 1014 connected in series between power supply potential Vcc and ground potential GND. An input signal is applied to the gates of both transistors. An output node is connected to respective drain nodes of these transistors.
Here, P channel MOS transistor 1012 attains a conductive state and N channel MOS transistor 1014 attains a disconnected state in response to an input of an L level to inverter 1010.
Similarly, P channel MOS transistor 1022, N channel MOS transistor 1034, and P channel MOS transistor 1042 in inverters 1020, 1030, and 1040, respectively, attain a cut off state.
As the integration density of recent semiconductor integrated circuit devices is increased, the size of transistors is scaled down. Accordingly, the power supply voltage is reduced in order to ensure reliability of the transistors by also scaling down the intensity of the electric field applied to each transistor.
This means that the logic threshold value of a logic gate is reduced. In other words, the threshold voltage of an N channel MOS transistor, for example, must be reduced.
More specifically, reduction in the voltage of an H level causes the necessity of ensuring the operating margin of an N channel MOS transistor to be cut off when a potential of an L level, for example, is applied to the gate.
However, this also induces degradation of the subthreshold characteristics of the N channel MOS transistor. A lower threshold voltage induces the problem that the leakage current of the N channel MOS transistor is increased when the gate potential thereof attains an L level.
The same can be said for a P channel MOS transistor.
FIGS. 18A and 18B are diagrams for describing the mechanism of leakage current increase in an N channel MOS transistor. FIG. 18A schematically shows the potential level of each element in a standby state where two inverters are connected in series. FIG. 18B shows the change in source-drain current with respect to gate voltage.
FIG. 18A shows only the first two stages of the inverter row shown in FIG. 17.
As described above, the input node of inverter 1010, i.e. the gate potential of N channel MOS transistor 1014, attains an L level in a standby state.
FIG. 18B shows the three cases where the threshold voltage is VT1, VT2, and 0V (VT1 greater than VT2 greater than 0V).
When the power supply voltage is, for example, 5V, a sufficient operating margin can be ensured even when the threshold voltage is VT1. Here, the source-drain current is its threshold leakage current Iso when gate voltage is 0V in order to render N channel MOS transistor 1014 non-conductive.
If the threshold voltage is lowered to the level of VT2 in order to ensure an operating margin when the power supply voltage is, for example, 3V, the leakage current of N channel MOS transistor 1014 attaining a cut off state increases. More specifically, the subthreshold leakage current when the gate potential is 0V increases from Iso to Is1.
The leakage current of the entire circuitry increases when the threshold voltage is lowered in order to operate at low voltage by decreasing the amount of impurity ions implanted into the channel region of a transistor.
In other words, there was a problem that the power consumption of an semiconductor integrated circuit device in a standby state is increased.
An object of the present invention is to provide an semiconductor integrated circuit device that does not have leakage current increased even when operated at a low power supply voltage, i.e. that does not have power consumption increased.
According to an aspect of the present invention, an semiconductor integrated circuit device includes an internal circuit, a first power source, a second power source, a plurality of first stage current control circuits, a plurality of second stage current control circuits, and an operating current control circuit.
The internal circuit includes a plurality of logic gates. The first power source supplies a first power supply potential corresponding to a first level of data processed by the internal circuit to a first power supply node. The second power source supplies a second power supply potential corresponding to a second level of data to a second power supply node. Each of the plurality of first stage current control circuits is provided between the logic gate and the first power supply node for controlling the amount of current flow from the first power source. Each of the plurality of second stage current control circuits is provided between the logic gate and the second power supply node for controlling the amount of current flow to the second power supply. The operating current control circuit controls the first and second stage current control circuits in response to the internal circuit attaining a standby state or an active state.
According to another aspect of the present invention, an semiconductor integrated circuit device includes an internal circuit, a first power source, a second power source, a plurality of stage current control circuits, and an operating current control circuit.
The internal circuit includes a plurality of CMOS control gates. The first power source supplies a first power supply potential corresponding to a first level of data processed by the internal circuit to a first power supply node. The second power source supplies a second power supply potential corresponding to a second level of data to a second power supply node. Each of the plurality of stage current control circuits is provided corresponding to the logic gate for controlling an amount of current flowing between one of the first power supply node and the second power supply node that is to be cut off from the output node of a corresponding logic gate according to a predetermined input signal level in a standby state and a corresponding logic gate. The operating current control circuit controls the stage current control circuit in response to the internal circuit attaining a standby state or an active state.
According to a further aspect of the present invention, an semiconductor integrated circuit device includes a plurality of internal circuit blocks, a control circuit, a first power source, a second power source, a plurality of first stage current control circuits, a plurality of second stage current control circuits, an operating current control circuit, a first switch circuit, and a second switch circuit.
The plurality of internal circuit blocks include a plurality of logic gates. The control circuit controls the operating timing of each internal circuit block. The first power source supplies a first power supply potential corresponding to a first level of data processed by the internal circuits. The second power supply supplies a second power supply potential corresponding to a second level of data. Each of the plurality of first stage current control circuits is provided corresponding to the CMOS logic circuit for controlling an amount of current flow from the first power source. Each of the plurality of second state current control circuits is provided corresponding to the logic gate for controlling an amount of current flow towards the second power source. The operating current control circuit controls the first and second stage current control circuits in response to the plurality of internal circuit blocks attaining a standby state or an active state. The first switch circuit is provided between the first power source and the plurality of first stage current control circuits for each internal circuit block, and controlled by the control circuit to be rendered conductive during an operating period of the internal circuit. The second switch circuit is provided between the second power source and the plurality of second state current control circuits for each internal circuit block, and controlled by the control circuit to be rendered conductive during an operating period of the internal circuit.
Thus, a main advantage of the present invention is that a self bias is applied to the transistor forming the logic gate in a direction where leakage current is reduced when there is a flow of leakage current via the logic gate during a standby period. Even when the threshold value of the transistor forming the logic gate is lowered in accordance with reduction in the power supply potential, power consumption of the logic gate in a standby state can be reduced.
Another advantage of the present invention is that the stage current control circuit is disposed at either the ground potential side or the power potential side according to the input signal of each logic gate attaining a predetermined level in the standby state. The number of the stage current control circuits can be suppressed to allow reduction in the layout area.
A further advantage of the present invention is that power consumption can further be reduced since operating current is supplied only to the logic gate circuit of the internal circuit attaining an active state out of the plurality of internal circuit blocks.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.